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Common-Gate J310 RF Amplifier

Interface mode
Schematic: Common-Gate J310 RF Amplifier

Bench sheet (PDF)Schematic PDFSPICE netlist (.cir)KiCad project (.zip)

  • gain_db 2 book
  • oip3_dbm 28 at 14 MHz book
  • nf_db 5.0 at 21 MHz book
  • s12_db -43 book
  • gain_db 2.0 at 14 MHz simulated
  • rl_db 13.9 at 14 MHz simulated

What it does

A low-gain, high-intercept RF amplifier for a receiver front end, with good reverse isolation (S12 about −43 dB). It keeps LO leakage off the antenna.

How it works

The J310 runs common gate, so its source presents a near-50 Ω input. A control voltage sets the drain current; the simulation shows current turning on above about 1.5 V and 13.6 mA at 2.0 V. T1 matches the drain to the 50 Ω output. R5 = 680 Ω loads the output for about 2 dB gain; omit it for about 6.5 dB (EMRFD p. 6.12).

Building it

  • Check the J310 pinout against your part's datasheet; the schematic pinout is unverified.
  • Adjust the control voltage for 12–14 mA drain current.

Tuning and testing

Measure drain current first. Then check gain and return loss with a signal generator and a return-loss bridge.

Where it comes from

A front-end amplifier from Experimental Methods in RF Design, Chapter 6.

Parts list

RefValueQty
C1,C20.1u2
J1RF IN1
J2RF OUT1
J3V control1
J4+12 V1
L12.7u1
Q1J3101
Q22N39041
R1,R61202
R2,R310K2
R41001
R56801
T115:5 t FT-37-431
SPICE netlist

References

  • EMRFD Fig 6.32, p. 6.12

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